It would be a good idea to set all (driven) variables to a known value. ![]() This allows for sin to be shifted out of sout ever clock cycle. What you really want is a loop where each iteration occurs on a new clock edge. The entire loop is executing in a single clock cycle, and the value of sout is only going to change once - to the value it was when the loop ended, which in this case is sin shifted by 4. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. ![]() ![]() In VHDL, a for loop executes in zero time. Library ieee use entity SReg is generic ( n: integer:= 4 ) port( clk: in stdlogic reset: in stdlogic enable: in stdlogic -enables shifting parallelin: in stdlogicvector(n-1 downto 0) sin: in stdlogic -serial input sout: out stdlogic -serial output ) end SReg architecture behavioral of SReg is signal tempreg: stdlogicvector(n-1 downto 0):= (Others = '0') begin process (clk,reset) begin if (reset = '1') then tempreg.
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